1. Field of the Invention
The present invention generally relates to a method of forming a shallow trench isolation (STI) region using a spacer material which also acts as a filler material.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. However, recent advances in technology have required deeper isolation regions driven by vertical transistors in DRAMs. Conventional methods have only allowed the shallow trench regions to reach depths of approximately 2500 .ANG. because it is not only difficult to etch a deep isolation with a resist mask but it is also difficult to fill it with oxide. There is therefore a desire for a method of forming deeper trench isolation regions.
It is noted that the longer the channel length of the vertical transistor transfer device, the lower the off-state leakage. This drives deeper isolation regions between the devices. It is well known in the art that deep trenches in the silicon may be etched with an oxide hardmask on top of the pad nitride (SiN). Further, recent advances with high density plasma (HDP) oxide fill allows oxide fill of isolation depths of about 4000 .ANG.. Thus, these deeper isolations require new and improved methods of fill.